1. Field of the Invention
The present invention relates to a synchronous semiconductor memory circuit and, more particularly, to a synchronous semiconductor memory circuit having an input register which captures input data at the voltage edge of each clock control signal.
2. Description of the Related Art
A synchronous memory has a clock input CLK which is a control signal for capturing or holding an input signal; a register or latch circuit provided for each input is controlled according to the foregoing control signal so as to eliminate the variations in respective input signals before introducing them inside. Once the input signals are taken in, changes in the input signals cause no problem because the input data can be held internally. To be more specific, storing operation is not affected by a shifted or reduced timing width of input information received from outside, thus making the synchronous memory suited for accomplishing higher operating frequencies. This concept is basically involved in designing a computer system; such a clock control register IC or the like has been installed in an input signal generating section of an synchronous memory. In recent years, there has been an increasing trend toward incorporating such a clock control register IC in the memory in order to achieve higher speed and also to reduce the number of ICs on a system board.
Referring to FIG. 6, a burst SRAM having an input register will be described as a conventional example of a synchronous memory circuit. The burst is a function for holding address data received from outside as it is, while generating a part of address data internally; this function is required for SRAM employed as a cache memory. A burst switching logic is added to a clock control path. An input address Add passes through an input buffer 1 and it is supplied as an internal signal A to a register circuit 5A.
A control signal CLK turns into an internal clock signal C via a buffer 3; likewise, a burst switching signal Burst turns into an internal signal B via a buffer 2. These signals B and C undergo the logical operation performed by a multiplexer 4B; the signals B and C turn into a register control clock CB via a buffer 10 before it is applied to a plurality of registers 5A. In an example of the circuit of the multiplexer 4B shown in FIG. 7, one of two input signals C1 and C2 is selected based on the control signal B. Pairs of a p-channel MOS transistor (pMOS) and an n-channel MOS transistor (nMOS) compose transfer switches 21 and 22, respectively. The selected transfer switch 21 or 22 based on the control signal B is turned ON so as to take out the selected input signal as an output CB. The input register 5A accepts the output A of the buffer 1 as input data; it is composed of a latch circuit 11, i.e. a master latch circuit, which uses the register control clock CB as a latch clock and another latch circuit 12, i.e. a slave latch circuit, which receives the output of the latch circuit 11 as input data thereof and uses the inverted signal of the register control clock CB, which has been issued by an inverter 13, as a latch clock. FIG. 8 shows an example of the latch circuits 11 and 12, wherein pMOS and nMOS serving as a transfer switch 31 are connected to an input IN, and the output thereof passes through an inverter 33 to provide an output OUT. At the same time, the signal of the output OUT is inverted by an inverter 34, then the inverted signal passes through the pMOS and nMOS of a transfer switch 32 to be fed back to the input end of the inverter 33. When the output CB is at low level, the transfer switch 31 turns ON and the transfer switch 32 turns OFF, thus setting a through mode. Conversely, when the output CB is at high level, the transfer switch 31 turns OFF and the transfer switch 32 turns ON, thus setting a latch mode by the flip-flop formed by the two inverters 33 and 34. An output A1 of the input register 5A provides an input signal of a decoder circuit 7A which passes through three AND gates 14, 15, and 16 to select a word line WL in this circuit example. It is necessary to add a signal CD for forming WL into a pulse signal to the signal applied to the last AND gate 16. For this purpose, a circuit method known as "pulse word" is used because, in the case of a synchronous system, the timing at which internal circuitry is actuated by the control signal CLK can be controlled, so that a memory cell is selected only for a required time. This method makes it possible to limit the time during which the circuit is in an activated state, permitting power saving or a longer time allowed for precharging of a digit line, contributing to higher speed. The pulse signal CD is generated as a one-shot pulse based on the internal clock C by a pulse generating circuit 6 and it is made via a delaying circuit 8B for adjusting timing. As shown by a circuit example in FIG. 9, the pulse generating circuit 6 is constituted by an input C and an AND gate 42 which accepts the output of an inverting logic circuit 41 serving also as a delay circuit.
The operation of the conventional circuit will be described with reference to FIG. 10 which shows a timing chart. The internal signal C of the control signal CLK is controlled by the internal signal B in the multiplexer 4B. Then the internal signal B is at the low level, data is accepted from outside, and the internal clock C is transferred to the output CB so that the signal is distributed to each register circuit 5A in a chip. When the internal signal B is at the high level, the burst mode is engaged; the output CB is fixed at the low level and therefore no data can be taken in from outside. The relationship of timing between the output CB and an address input A coming into the input register 5A is represented by setup ts and hold tH in the chart. Ideally, the timing margin is maintained so that ts and t.sub.H are equal. The output CB has a large delay because it actuates all the input registers 5A, while the internal signal A has a small delay because it actuates only one input buffer. Hence, the signal CB is designed to be the quickest and the internal signal A is delayed to make adjustment according to the signal CB. In the input register 5A, at the rising edge of the output CB, the master latch circuit 11 in a first stage changes from the through mode to the latch mode to hold data; at the same time, the slave latch circuit 12 in the following stage unlatches the retained data of the preceding cycle, and new data of the master latch circuit 11 in the first stage is transferred internally in the through mode. This operation captures the input address Add at the edge of the control signal CLK; the time elapsed from the signal CB to the signal A1 is the delay time at the input register 5A. The time elapsed from the internal signal A1 to an internal signal A3 is the delay time at the decoding circuit 7A; the pulse signal CD must be later than the signal A3. More specifically, without timing margin tm, a selected pulse would undesirably be issued after the pulse of preceding data is issued, resulting in multiple selection or variations in pulse width. To secure the time margin tm, a pulse signal CP produced by the pulse generating circuit 6 need to be provided with delay by the delay circuit 8B. In this way, the WL pulse always starts and ends at the timing determined by the CD pulse, ensuring stable pulse operation independent of a cycle time.
In the conventional synchronous memory circuit described above, the delay of the critical path from the input of the control signal CLK to the WL selection involved in the section from the input register 5A to the decoder circuit 7A for the pulse word selection may be represented by the total of the delay elements shown below:
1. From the input of the control signal CLK to the generation of the internal clock C: CLK.fwdarw.C PA0 2. Distribution to the multiplexer 4B and all the input registers 5A: C.fwdarw.CB PA0 3. Output delay of the registers 5A: CB.fwdarw.A1 PA0 4. Delay of decoder: A1.fwdarw.A3 PA0 5. Timing margin relative to pulse signal A3: tm PA0 6. Delay of the word driver in the last stage: CD.fwdarw.WL
The circuitry must be designed to minimize the total of the above delay elements to achieve higher speed; however, merely minimizing the total delay is not enough for accomplishing markedly higher speed. Achieving higher speed of the critical path is becoming indispensable for realizing a synchronous memory which operates at a higher operating frequency.